FDSOI devices with thin BOX and ground plane integration for 32nm node and below

In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well situated for low power (LP) applications. The different BOX thicknesses and g...

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Main Authors: Fenouillet-Beranger, C., Denorme, S., Perreau, P., Buj, C., Faynot, O., Andrieu, F., Tosti, L., Barnola, S., Salvetat, T., Garros, X., Casse, M., Allain, F., Loubet, N., Pham-NGuyen, L., Deloffre, E., Gros-Jean, M., Beneyton, R., Laviron, C., Marin, M., Leyris, C., Haendler, S., Leverd, F., Gouraud, P., Scheiblin, P., Clement, L., Pantel, R., Deleonibus, S., Skotnicki, T.
Format: Conference Proceeding
Language:English
Subjects:
Annealing
CMOS technology
Electrostatics
Epitaxial growth
Fabrication
High-K gate dielectrics
MOS devices
Thin film devices
Threshold voltage
Tin
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Summary:In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well situated for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk shrunk technology in terms of variability and noise. 0.499 mum 2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1V.
ISSN:1930-8876
DOI:10.1109/ESSDERC.2008.4681734