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Boundary-Scan Testing of Power/Ground Pins
Most integrated circuits today possess large numbers of power and ground pins in addition to signal pins. Boundary-scan technology will adequately test the signals, but in general does not address open defects on the power/ground pins. Some ICs could get at least partial coverage on some of these pi...
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creator | Parker, K.P. Jacobson, N.G. |
description | Most integrated circuits today possess large numbers of power and ground pins in addition to signal pins. Boundary-scan technology will adequately test the signals, but in general does not address open defects on the power/ground pins. Some ICs could get at least partial coverage on some of these pins due to their internal power/ground distribution structure. Thus boundary-scan could be used to test, diagnose and claim coverage for these defects. What is needed is an extension to BSDL to support this capability. |
doi_str_mv | 10.1109/TEST.2008.4700628 |
format | conference_proceeding |
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Boundary-scan technology will adequately test the signals, but in general does not address open defects on the power/ground pins. Some ICs could get at least partial coverage on some of these pins due to their internal power/ground distribution structure. Thus boundary-scan could be used to test, diagnose and claim coverage for these defects. What is needed is an extension to BSDL to support this capability.</description><identifier>ISSN: 1089-3539</identifier><identifier>ISBN: 9781424424023</identifier><identifier>ISBN: 142442402X</identifier><identifier>EISSN: 2378-2250</identifier><identifier>EISBN: 1424424038</identifier><identifier>EISBN: 9781424424030</identifier><identifier>DOI: 10.1109/TEST.2008.4700628</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit testing ; Educational institutions ; Integrated circuit modeling ; Integrated circuit packaging ; Integrated circuit technology ; Integrated circuit testing ; Jacobian matrices ; Pins ; Power engineering and energy ; Rails</subject><ispartof>2008 IEEE International Test Conference, 2008, p.1-8</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4700628$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,778,782,787,788,2054,27908,54538,54903,54915</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4700628$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Parker, K.P.</creatorcontrib><creatorcontrib>Jacobson, N.G.</creatorcontrib><title>Boundary-Scan Testing of Power/Ground Pins</title><title>2008 IEEE International Test Conference</title><addtitle>TEST</addtitle><description>Most integrated circuits today possess large numbers of power and ground pins in addition to signal pins. Boundary-scan technology will adequately test the signals, but in general does not address open defects on the power/ground pins. Some ICs could get at least partial coverage on some of these pins due to their internal power/ground distribution structure. Thus boundary-scan could be used to test, diagnose and claim coverage for these defects. What is needed is an extension to BSDL to support this capability.</description><subject>Circuit testing</subject><subject>Educational institutions</subject><subject>Integrated circuit modeling</subject><subject>Integrated circuit packaging</subject><subject>Integrated circuit technology</subject><subject>Integrated circuit testing</subject><subject>Jacobian matrices</subject><subject>Pins</subject><subject>Power engineering and energy</subject><subject>Rails</subject><issn>1089-3539</issn><issn>2378-2250</issn><isbn>9781424424023</isbn><isbn>142442402X</isbn><isbn>1424424038</isbn><isbn>9781424424030</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1j0tLw0AUhccXmNb-AHGTtTDpnXvnudRSa6HQQrMvmc6NRDSRpCL-eytWOHAWH3ycI8StgkIpCNNyvi0LBPCFdgAW_ZkYKY36GCB_LjIk5yWigQsxCc7_M6RLkSnwQZKhcC1Gw_AKgGAQMnH_2H22qeq_5XZftXnJw6FpX_KuzjfdF_fTRf_L803TDjfiqq7eBp6ceizKp3k5e5ar9WI5e1jJJsBBWuuSNzF4F4wGCy6CSxwZbECwBvbGVklHDhWRYkxITIliBOCatLU0Fnd_2oaZdx99835ctztdph8U3UPm</recordid><startdate>200810</startdate><enddate>200810</enddate><creator>Parker, K.P.</creator><creator>Jacobson, N.G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200810</creationdate><title>Boundary-Scan Testing of Power/Ground Pins</title><author>Parker, K.P. ; Jacobson, N.G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-667d85b9879540607b07debe06920650c56ad4be9a331e2d23e3d3bb00ef34663</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Circuit testing</topic><topic>Educational institutions</topic><topic>Integrated circuit modeling</topic><topic>Integrated circuit packaging</topic><topic>Integrated circuit technology</topic><topic>Integrated circuit testing</topic><topic>Jacobian matrices</topic><topic>Pins</topic><topic>Power engineering and energy</topic><topic>Rails</topic><toplevel>online_resources</toplevel><creatorcontrib>Parker, K.P.</creatorcontrib><creatorcontrib>Jacobson, N.G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Parker, K.P.</au><au>Jacobson, N.G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Boundary-Scan Testing of Power/Ground Pins</atitle><btitle>2008 IEEE International Test Conference</btitle><stitle>TEST</stitle><date>2008-10</date><risdate>2008</risdate><spage>1</spage><epage>8</epage><pages>1-8</pages><issn>1089-3539</issn><eissn>2378-2250</eissn><isbn>9781424424023</isbn><isbn>142442402X</isbn><eisbn>1424424038</eisbn><eisbn>9781424424030</eisbn><abstract>Most integrated circuits today possess large numbers of power and ground pins in addition to signal pins. Boundary-scan technology will adequately test the signals, but in general does not address open defects on the power/ground pins. Some ICs could get at least partial coverage on some of these pins due to their internal power/ground distribution structure. Thus boundary-scan could be used to test, diagnose and claim coverage for these defects. What is needed is an extension to BSDL to support this capability.</abstract><pub>IEEE</pub><doi>10.1109/TEST.2008.4700628</doi><tpages>8</tpages></addata></record> |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Circuit testing Educational institutions Integrated circuit modeling Integrated circuit packaging Integrated circuit technology Integrated circuit testing Jacobian matrices Pins Power engineering and energy Rails |
title | Boundary-Scan Testing of Power/Ground Pins |
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