A floorplanning algorithm for block placement in SoC design

With the dramatic increase in size and complexity of systems on chip (SoC), there might be as much as hundreds of macro blocks and millions of standard cells integrated into a single chip. To facilitate signal routing and P/G network construction, one approach is to place macros around the boundary...

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Bibliographic Details
Main Authors: Shanshan Chen, Linkai Wang, Xiaofang Zhou
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Automatic testing
Circuit testing
Integrated circuit interconnections
Laboratories
Pins
Routing
Simulated annealing
System-on-a-chip
Timing
Online Access:Request full text
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Summary:With the dramatic increase in size and complexity of systems on chip (SoC), there might be as much as hundreds of macro blocks and millions of standard cells integrated into a single chip. To facilitate signal routing and P/G network construction, one approach is to place macros around the boundary of chip and the remainder is used for arrangement of standard cells. To deal with such kind of placement, we propose an algorithm based on simulated annealing using B*-tree. The proposed algorithm guarantees a feasible solution through perturbation of B*-tree and the experimental results prove it very efficient.
DOI:10.1109/ICSICT.2008.4735022