A novel packing algorithm for sparse crossbar FPGA architectures

The cluster-based FPGA can significantly improve timing and routability. Packing is introduced in the CAD flow to pack logic elements into clusters. In order to reduce unnecessary connectivity within a cluster, sparse crossbar FPGA architectures are under investigation. This paper proposes a novel p...

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Bibliographic Details
Main Authors: Kanwen Wang, Meng Yang, Lingli Wang, Xuegong Zhou, Jiarong Tong
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Clustering algorithms
Delay
Feedback
Field programmable gate arrays
Logic design
Multiplexing
Routing
Switches
Timing
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Summary:The cluster-based FPGA can significantly improve timing and routability. Packing is introduced in the CAD flow to pack logic elements into clusters. In order to reduce unnecessary connectivity within a cluster, sparse crossbar FPGA architectures are under investigation. This paper proposes a novel packing algorithm using direct graph searching method and connection gain function. Experimental results show that half populated crossbar FPGA architecture achieves 7% area improvement compared to fully populated counterpart with only 3% number of external nets overhead.
DOI:10.1109/ICSICT.2008.4735050