Pipelined Lifting-Based VLSI Architecture for Two-Dimensional Inverse Discrete Wavelet Transform

In this paper, high performance pipelined VLSI architectures for both inverse 5/3 and 9/7 filters and combined 5/3 and 9/7 are proposed. To ease architecture development the strategy adopted is to divide the details of the development into two steps each having less information to handle. In the fir...

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Bibliographic Details
Main Authors: Koko, I.S., Agustiawan, H.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Decorrelation
Discrete wavelet transforms
Filters
High performance computing
Image coding
Image reconstruction
inverse discrete wavelet transform
lifting scheme and JPEG2000
pipelined VLSI architecture
Transform coding
Two dimensional displays
Very large scale integration
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Summary:In this paper, high performance pipelined VLSI architectures for both inverse 5/3 and 9/7 filters and combined 5/3 and 9/7 are proposed. To ease architecture development the strategy adopted is to divide the details of the development into two steps each having less information to handle. In the first step, the external architecture, which is identical for both 5/3 and 9/7 and consists of a column-processor (CP) and a row-processor (RP), is developed. In the second step, fully pipelined column and row processors datapath architectures for 5/3 and 9/7 are developed separately that fit into CP and RP of the external architecture. The architecture also implements the symmetric extension algorithm recommended by JPEG2000.
DOI:10.1109/ICCEE.2008.14