A first-level calorimeter trigger for the ATLAS experiment

In the RD27 collaboration we have carried out system studies on the implementation of the first level calorimeter trigger processor system for the ATLAS experiment to be mounted at the Large Hadron Collider (LHC) at CERN. These studies suggest that the full system can be contained in six 18SU size c...

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Bibliographic Details
Main Authors: Perera, V., Edwards, J., Gee, N., Gillman, A., Hatley, R., Leake, J., Quinton, S., Shah, T.P., Eisenhandler, E., Landon, M., Brawn, I., Carney, R., Garvey, J., Staley, R., Watson, A., Ellis, N.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Collaboration
Delay
Electrons
Large Hadron Collider
Optical design
Photonic integrated circuits
Pins
Prototypes
Signal processing
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Summary:In the RD27 collaboration we have carried out system studies on the implementation of the first level calorimeter trigger processor system for the ATLAS experiment to be mounted at the Large Hadron Collider (LHC) at CERN. These studies suggest that the full system can be contained in six 18SU size crates which will process approximately 4000 electromagnetic and 4000 hadronic trigger cells and provide the central trigger processor (CTP) with signals from events with high-P/sub T/ electrons/photons, jets and missing-E/sub T/. A demonstrator trigger system operated successfully with the RD3 and RD33 calorimeters at the full 40 MHz LHC bunch crossing (BC) rate. The prototype application-specific integrated circuits (ASICs) in this system each processed data from only a single trigger cell and it's environment, which would lead to an extremely large system for ATLAS. Using eight-bit parallel data even the use ASICs, processing multiple trigger cells would demand unacceptably large numbers of input pins and module connections. Initial studies of this I/O problem produced a solution based on asynchronous transmission of zero-suppressed and BC-tagged data on 160 Mbit/s serial links [2]. This approach appeared to be feasible but would have introduced additional latency of about 20 BCs. Further studies have led to the design of a fully-synchronous calorimeter trigger processor system using commercial high-speed optical links. The links will terminate in multi-chip modules (MCMs) incorporating custom-designed integrated optics, and the trigger algorithms will be implemented in ASICs.< >
DOI:10.1109/NSSMIC.1994.474485