Application Specific Instruction set processor specialized for block motion estimation

This paper presents a novel application specific instruction set processor specialized for block motion estimation. The proposed architecture includes an efficient register file system in terms of data reuse and parallel processing. Performances and area costs are presented for different levels of p...

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Bibliographic Details
Main Authors: Daigneault, M.-A., Langlois, J.M.P., David, J.P.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Application specific processors
Bandwidth
Computer architecture
Field programmable gate arrays
Hardware
Motion estimation
Parallel processing
Registers
Systolic arrays
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Description
Summary:This paper presents a novel application specific instruction set processor specialized for block motion estimation. The proposed architecture includes an efficient register file system in terms of data reuse and parallel processing. Performances and area costs are presented for different levels of parallelism and register file dimensions. Various FPGA implementations of the architecture are further studied in order to present the most important factors affecting performance and hardware resource utilization. The proposed instruction extension block architecture enables acceleration by 3 orders of magnitude for full-search block matching algorithms.
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2008.4751872