Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation

This paper presents two area-efficient algorithms and their architectures based on CORDIC. While the first algorithm eliminates ROM and requires only low-complexity barrel shifters, the second eliminates barrel shifters completely. As a consequence, both the algorithms consume approximately 50% area...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2009-01, Vol.56 (1), p.61-65
Main Authors: Vachhani, L., Sridharan, K., Meher, P.K.
Format: Article
Language:English
Subjects:
Algorithm design and analysis
Algorithms
Architecture
Barrel shifter
Circuits
Consumption
Convergence
coordinate rotation digital computer (CORDIC)
Design engineering
Effectiveness
extended range
Field programmable gate arrays
Hardware
low area and high throughput implementation
Multiplexing
Phase estimation
Read only memory
Table lookup
Throughput
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Summary:This paper presents two area-efficient algorithms and their architectures based on CORDIC. While the first algorithm eliminates ROM and requires only low-complexity barrel shifters, the second eliminates barrel shifters completely. As a consequence, both the algorithms consume approximately 50% area in comparison with other CORDIC designs. Further, the proposed algorithms are applicable to the entire range of angles. The FPGA implementations consume approximately 8% LUTs of a Xilinx Spartan XC2S200E device and have a slice-delay product of about 3. Convergence proofs for the algorithms are presented. Experimental comparisons with prior CORDIC designs confirm the efficacy of the proposed designs.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2008.2010169