On the optimization of hierarchical redundancies including configuration nets and switches

• Main Author: Iden, H.-J.M.
• Format: Conference Proceeding
• Language: English
• Subjects: Circuits; Cost function; Knowledge based systems; Minimization; Production; Semiconductor device modeling; Silicon; Switches; Wafer scale integration
• DOI: 10.1109/WAFER.1989.47548

The optimization of hierarchical redundancies for large-area monolithic wafer-scale integration systems is discussed. Optimality is defined by a cost function, which accounts for yield as well as for area. On the basis of this cost function, the optimal implementation of redundancy for each part of a system is described analytically. Thus, the redundancy needed for a certain part of a system can be calculated simply instead of by doing a numerical multiparameter optimization for the whole system. For a subset of modules called 'critical', an exact solution is given. For the general case of a module in a hierarchy, an estimation is given. It has to be based on certain assumptions, which are related to the important influence of configuration nets and switches. Results calculated from the analytical description fit those obtained by a numerical optimization. The analytical descriptions give an insight into the properties of optimized redundant systems, their dependency on defect density, and their overhead, depending on system size.< >