An iterative approximation for the charge-storage capacity of MOS capacitors with an application to DRAM trench capacitor memory cells

• Published in: IEEE transactions on electron devices 1995-12, Vol.42 (12), p.2217-2225
• Main Authors: Perry, R.J., Uyemura, J.P.
• Format: Article
• Language: English
• Subjects: Circuit simulation; Closed-form solution; Computational efficiency; Computational modeling; Equations; MOS capacitors; Numerical simulation; Predictive models; Random access memory; Semiconductor devices
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.477782

An iterative approximation based on the charge-sheet model which calculates the charge-storage capacity of a metal-oxide-semiconductor (MOS) capacitor is presented. The iterative approximation combines the numerical accuracy available from two-dimensional semiconductor device simulations with the computational efficiency normally associated with closed-form solutions. In addition, under certain process and bias conditions, the iterative solution predicts behavior not demonstrated by the closed-form equations, but verified by results obtained from device simulations. The approximation is therefore useful in the design of MOS-based circuits when quick but accurate estimations of charge-storage capacity are required. The iterative approximation is applied to estimate the charge-storage capacity of a variety of dynamic random-access memory (DRAM) trench capacitor cells. Several examples comparing charge-storage capacity approximations obtained from numerical semiconductor device simulations, closed-form solutions, and the proposed iterative approximation are given for inversion-store (IST), diffusion-store (DST), substrate-plate (SPT), and stacked (ST) trench-type DRAM cells. As expected, the iterative solution consistently produces results that compared favorable to the results obtained from numerical device simulations but at a much lower computational cost.