Reliability Guard Band Reduction by Differential Targeting of pMOS Gate Oxide Thickness

In the presented work we demonstrate an efficient way to improve the balance between performance and reliability in the case that microprocessor speed is limited by a pMOS dominated speed path. It is shown that with differential targeted, thicker pMOS gate oxide thickness (TOX), realized by the sele...

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Bibliographic Details
Main Authors: Geilenkeuser, R., Wieczorek, K., Trentzsch, M., Graetsch, F., Bayha, B., Samohvalov, V., Paetzold, T., Schink, T.
Format: Conference Proceeding
Language:English
Subjects:
Degradation
Frequency
Human computer interaction
Microprocessors
MOS devices
Niobium compounds
Stress
Testing
Titanium compounds
Voltage
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Summary:In the presented work we demonstrate an efficient way to improve the balance between performance and reliability in the case that microprocessor speed is limited by a pMOS dominated speed path. It is shown that with differential targeted, thicker pMOS gate oxide thickness (TOX), realized by the selective control of nMOS and pMOS GOX, pMOS degradation in terms of HCI and NBTI can be effectively reduced at tolerable loss of initial product frequency. Fast Wafer Level Reliability (fWLR) techniques are used as an effective tool to quickly characterize the thickness dependence of the degradation components. Product wearout experiments confirm that less product frequency degradation is observed with a thicker P-TOX, which is in agreement with the degradation of ringoscillator frequency as well, stressed in parallel to the product.
ISSN:1930-8841
2374-8036
DOI:10.1109/IRWS.2008.4796096