A multi-task-oriented security processing architecture with powerful extensibility

A multi-task-oriented security processing architecture is presented in this paper. This architecture contains a host microprocessor and multiple security processors (SP). The SP could integrate dedicated Crypto-Engines, which provides functional extensibility. And the performance scalability and mul...

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Bibliographic Details
Main Authors: Dan Cao, Jun Han, Xiao-yang Zeng, Shi-ting Lu
Format: Conference Proceeding
Language:English
Subjects:
CMOS technology
Communication system security
Cryptography
Data security
Data structures
Power system security
Scalability
Switches
System buses
Testing
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Summary:A multi-task-oriented security processing architecture is presented in this paper. This architecture contains a host microprocessor and multiple security processors (SP). The SP could integrate dedicated Crypto-Engines, which provides functional extensibility. And the performance scalability and multi-task parallelism could be enhanced by increasing the number of SPs on system bus. It's demonstrated that this architecture greatly improves the system efficiency. A test chip is implemented based on SMIC 0.18 um standard CMOS technology, and its functionality is well verified.
ISSN:2153-6961
2153-697X
DOI:10.1109/ASPDAC.2009.4796468