Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Negative bias temperature instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in NM...

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Bibliographic Details
Main Authors: Kumar, S.V., Kim, C.H., Sapatnekar, S.S.
Format: Conference Proceeding
Language:English
Subjects:
Aging
Degradation
Digital circuits
Gate leakage
High-K gate dielectrics
MOSFETs
Negative bias temperature instability
Niobium compounds
Titanium compounds
Voltage
Online Access:Request full text
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Summary:Negative bias temperature instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guard-bands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.
ISSN:2153-6961
2153-697X
DOI:10.1109/ASPDAC.2009.4796494