Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture

To solve recent pressing issues regarding satisfying numerous video codec standards and supporting ldquofull-high-definitionrdquo (full-HD) (i.e., 1920 pixels by 1080 lines) video on different consumer devices, a multi-standard CODEC IP based on a heterogeneous multiprocessor architecture was develo...

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Bibliographic Details
Main Authors: Nakata, Hiroaki, Hosogi, Koji, Ehama, Masakazu, Yuasa, Takafumi, Fujihira, Toru, Iwata, Kenichi, Kimura, Motoki, Izuhara, Fumitaka, Mochizuki, Seiji, Nobori, Masaki
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Code standards
Energy consumption
Frequency
MPEG 4 Standard
Pressing
Process design
Standards development
Streaming media
Video codecs
Online Access:Request full text
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Summary:To solve recent pressing issues regarding satisfying numerous video codec standards and supporting ldquofull-high-definitionrdquo (full-HD) (i.e., 1920 pixels by 1080 lines) video on different consumer devices, a multi-standard CODEC IP based on a heterogeneous multiprocessor architecture was developed. To achieve satisfactory performance with low power consumption, operation-specific processors were designed in regards to two types of processing: stream processing and pixel processing. The CODEC uses effectively several dedicated circuits for functions which are unsuitable for those processors. To design the CODEC, we developed a C-language model to check that the architecture worked correctly. The model was also used as a reference for verifying the RTL model. The CODEC can process full-HD videos formatted in H.264, MPEG-2, MPEG-4, and VC-1 at an operating frequency of 162 MHz.
ISSN:2153-6961
2153-697X
DOI:10.1109/ASPDAC.2009.4796534