Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and high-k/metal gate stack for monolithic 3D integration

• Main Authors: Jin-Hong Park, Tada, M., Kuzum, D., Kapur, P., Hyun-Yong Yu, Wong, H.-S.P., Saraswat, K.C.
• Format: Conference Proceeding
• Language: English
• Subjects: CMOS process; CMOS technology; Crystallization; Electron mobility; High K dielectric materials; High-K gate dielectrics; Inorganic materials; MOSFET circuits; Temperature; Three-dimensional integrated circuits
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2008.4796702

We demonstrate high performance, 3D IC compatible, Ge n and p-MOSFETs fabricated at very low temperatures, below 380degC. The low temperature gate stack comprises of high-K/metal materials. Very low series resistance (2.23times10 -4 Omega-cm at the lowest point of SRP) and shallow (92 nm) source/drain (S/D) junctions with high degree of dopant activation is achieved especially in n-MOSFETs using CMOS process compatible technique - metal (Co) induced dopant activation (Co MIDA) and Ge crystallization. Low S/D resistance in Ge n-MOSFETs has previously been highly challenging. The Ge n-MOSFET, fabricated at 360degC, has an electron mobility comparable to the highest one reported previously, while the Ge p-MOSFET shows a hole mobility higher than the universal Si mobility. The Ge n- and p-MOSFETs provide an excellent I on /I off ratio ( ~1.1times10 3 for both). In addition to other uses, this low temperature Ge CMOS process serves as a compelling enabler for integrating high performance Ge transistors above metal layers as required by 3D-ICs without exceeding 400degC.