A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

• Main Authors: Jan, C.-H., Bai, P., Biswas, S., Buehler, M., Chen, Z.-P., Curello, G., Gannavaram, S., Hafez, W., He, J., Hicks, J., Jalan, U., Lazo, N., Lin, J., Lindert, N., Litteken, C., Jones, M., Kang, M., Komeyli, K., Mezhiba, A., Naskar, S., Olson, S., Park, J., Parker, R., Pei, L., Post, I., Pradhan, N., Prasad, C., Prince, M., Rizk, J., Sacks, G., Tashiro, H., Towner, D., Tsai, C., Wang, Y., Yang, L., Yeh, J.-Y., Yip, J., Mistry, K.
• Format: Conference Proceeding
• Language: English
• Subjects: CMOS logic circuits; CMOS technology; High K dielectric materials; High-K gate dielectrics; Logic gates; MOS devices; Power systems; Radio frequency; Silicon; System-on-a-chip
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2008.4796772

A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured f T /f MAX values of 395 GHz/410 GHz for NMOS and 300 GHz/325 GHz for PMOS with 28 nm L gate transistors. HV I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OTP fuses are employed for HV I/O, analog and RF circuit integration.