AND-XOR Network Synthesis with Area-Power Trade-off

As AND-XOR network results in much better realization and requires fewer product terms than AND-OR realization, it network has encouraged researchers to look for efficient minimization and synthesis tools for their realization. Among several canonical representations of AND-XOR networks, popular and...

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Bibliographic Details
Main Authors: Pradhan, S.N., Chattopadhyay, S.
Format: Conference Proceeding
Language:English
Subjects:
Boolean functions
Circuit synthesis
Circuit testing
Combinational circuits
Delay
Field programmable gate arrays
Genetic algorithms
Minimization
Network synthesis
Space technology
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Summary:As AND-XOR network results in much better realization and requires fewer product terms than AND-OR realization, it network has encouraged researchers to look for efficient minimization and synthesis tools for their realization. Among several canonical representations of AND-XOR networks, popular and most testable one is the fixed polarity Reed Muller (FPRM) form. In this paper we have used GA (genetic algorithm) to select the polarities of the variables of the AND-XOR network. The polarity is selected based on the optimization of area, dynamic power and leakage power of the resulting circuit. This is the first ever effort to incorporate leakage power consideration in the variable polarity selection process. Here, we have presented new leakage power model of AND, OR and XOR gates at 90nm technology. The area (in terms of number of product terms) results obtained are superior to those reported in the literature. It also enumerates the trade-offs present in the solution space for different weights associated with area, dynamic power and leakage power of the resulting AND-XOR network.
ISSN:2164-7011
2690-3423
DOI:10.1109/ICIINFS.2008.4798440