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Thermo-mechanical reliability considerations with dynamic voltage/frequency scaling in microprocessor applications
With each advancing generation of process technology, the CPU power continues to rise, creating additional issues for thermal/mechanical packaging design. A common theme in next-generation CPU offerings will be the use of dynamic voltage and frequency scaling (DVFS) to manage the chip power during o...
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Main Authors: | , |
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Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
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Summary: | With each advancing generation of process technology, the CPU power continues to rise, creating additional issues for thermal/mechanical packaging design. A common theme in next-generation CPU offerings will be the use of dynamic voltage and frequency scaling (DVFS) to manage the chip power during operation. With a DVFS policy, it becomes all the more important to study the potential impacts of imposed temporal variation in power on the thermo-mechanical reliability. In this study, we demonstrate a system identification approach for a practical CPU application and exemplify the trade-offs involved in creating a DVFS policy that is satisfactory to both thermal/mechanical reliability engineers and CPU design teams. |
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ISSN: | 1065-2221 2577-1000 |
DOI: | 10.1109/STHERM.2009.4810754 |