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CPU dynamic thermal management via thermal spare cores
Adding cores to CPU chip increases its power density and leads to thermal throttling due to cooling limitations. Thermal spare cores (TSC) is proposed as new technique for dynamic thermal management (DTM). Our objective is to avoid thermal throttling and ensure stable CPU performance. Towards this o...
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| creator | Elsawaf, M.A. Fahmy, H.A. Elshafei, A.L. |
| description | Adding cores to CPU chip increases its power density and leads to thermal throttling due to cooling limitations. Thermal spare cores (TSC) is proposed as new technique for dynamic thermal management (DTM). Our objective is to avoid thermal throttling and ensure stable CPU performance. Towards this objective, thermal model of IBM Power 4 CPU chip contains 8 cores implemented as proof of concept. TSC higher potential expected with CUP chip having higher number of cores under thermal constraints. In the near future we will be able to add dozens of cores to CUP chip; while we will not be able to activate them all simultaneously due to air cooling limitations and thermal throttling. |
| doi_str_mv | 10.1109/STHERM.2009.4810755 |
| format | conference_proceeding |
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Thermal spare cores (TSC) is proposed as new technique for dynamic thermal management (DTM). Our objective is to avoid thermal throttling and ensure stable CPU performance. Towards this objective, thermal model of IBM Power 4 CPU chip contains 8 cores implemented as proof of concept. TSC higher potential expected with CUP chip having higher number of cores under thermal constraints. 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In the near future we will be able to add dozens of cores to CUP chip; while we will not be able to activate them all simultaneously due to air cooling limitations and thermal throttling.</description><subject>Central Processing Unit</subject><subject>Clocks</subject><subject>Control systems</subject><subject>Cooling</subject><subject>Dynamic voltage scaling</subject><subject>Energy management</subject><subject>Temperature</subject><subject>Thermal engineering</subject><subject>Thermal management</subject><subject>Very large scale integration</subject><issn>1065-2221</issn><issn>2577-1000</issn><isbn>1424436648</isbn><isbn>9781424436644</isbn><isbn>9781424436651</isbn><isbn>1424436656</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo9j91Kw0AUhNc_MK19gt7kBRLP2eTsZi8lVCtUFG2vy0n2rEaaWJIg9O0tWL0amPmYYZSaI6SI4G7f1svF61OqAVyaFwiW6EzNnC0w13meGUN4riJN1iYIABdq8hfkxaWKEAwlWmu8VpNh-DwSVhuKlClfNrE_dNw2dTx-SN_yLm6543dppRvj74b_7WHPvcT1Vy_DjboKvBtkdtKp2twv1uUyWT0_PJZ3q6RBS2OibR0MO-us0QIctK5dRZX3x3FAT74OzofARjizhSFwVeaEcl9JhTZQNlXz395GRLb7vmm5P2xP_7Mffa5K3w</recordid><startdate>200903</startdate><enddate>200903</enddate><creator>Elsawaf, M.A.</creator><creator>Fahmy, H.A.</creator><creator>Elshafei, A.L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200903</creationdate><title>CPU dynamic thermal management via thermal spare cores</title><author>Elsawaf, M.A. ; Fahmy, H.A. ; Elshafei, A.L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-27cf6a979762e0af22c9b5bdd72601d5dcf9dffa6ea3786509b39e54dbeb17f53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Central Processing Unit</topic><topic>Clocks</topic><topic>Control systems</topic><topic>Cooling</topic><topic>Dynamic voltage scaling</topic><topic>Energy management</topic><topic>Temperature</topic><topic>Thermal engineering</topic><topic>Thermal management</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Elsawaf, M.A.</creatorcontrib><creatorcontrib>Fahmy, H.A.</creatorcontrib><creatorcontrib>Elshafei, A.L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore (Online service)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Elsawaf, M.A.</au><au>Fahmy, H.A.</au><au>Elshafei, A.L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>CPU dynamic thermal management via thermal spare cores</atitle><btitle>2009 25th Annual IEEE Semiconductor Thermal Measurement and Management Symposium</btitle><stitle>STHERM</stitle><date>2009-03</date><risdate>2009</risdate><spage>139</spage><epage>145</epage><pages>139-145</pages><issn>1065-2221</issn><eissn>2577-1000</eissn><isbn>1424436648</isbn><isbn>9781424436644</isbn><eisbn>9781424436651</eisbn><eisbn>1424436656</eisbn><abstract>Adding cores to CPU chip increases its power density and leads to thermal throttling due to cooling limitations. Thermal spare cores (TSC) is proposed as new technique for dynamic thermal management (DTM). Our objective is to avoid thermal throttling and ensure stable CPU performance. Towards this objective, thermal model of IBM Power 4 CPU chip contains 8 cores implemented as proof of concept. TSC higher potential expected with CUP chip having higher number of cores under thermal constraints. In the near future we will be able to add dozens of cores to CUP chip; while we will not be able to activate them all simultaneously due to air cooling limitations and thermal throttling.</abstract><pub>IEEE</pub><doi>10.1109/STHERM.2009.4810755</doi><tpages>7</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1065-2221 |
| ispartof | 2009 25th Annual IEEE Semiconductor Thermal Measurement and Management Symposium, 2009, p.139-145 |
| issn | 1065-2221 2577-1000 |
| language | eng |
| recordid | cdi_ieee_primary_4810755 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Central Processing Unit Clocks Control systems Cooling Dynamic voltage scaling Energy management Temperature Thermal engineering Thermal management Very large scale integration |
| title | CPU dynamic thermal management via thermal spare cores |
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