Energy-effective design & implementation of an embedded VLIW DSP

This paper describes the power/energy optimizations of an embedded VLIW digital signal processor (DSP) - PACDSP from the Industrial Technology Research Institute (ITRI). First, a configurable cache/scratchpad memory subsystem has been implemented, which saves the energy for tag matching in deeply em...

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Bibliographic Details
Main Authors: Tien-Wei Hsieh, Pi-Chen Hsiao, Che-Yu Liao, Hsien-Ching Hsieh, Huang-Lun Lin, Tay-Jyi Lin, Yuan-Hua Chu, An-Yeu Wu
Format: Conference Proceeding
Language:English
Subjects:
CMOS technology
Digital signal processing
Digital signal processors
Dynamic voltage scaling
embedded processor
Energy efficiency
Frequency
Industrial relations
Power dissipation
Testing
VLIW
VLIW DSP
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Summary:This paper describes the power/energy optimizations of an embedded VLIW digital signal processor (DSP) - PACDSP from the Industrial Technology Research Institute (ITRI). First, a configurable cache/scratchpad memory subsystem has been implemented, which saves the energy for tag matching in deeply embedded applications. An energy-effective cell-based design has been produced by analyzing the relationships between the energy efficiency and the synthesis constraints. Finally, dynamic voltage & frequency scaling (DVFS) and power gating have been applied to reduce both switching and leakage power dissipations with a novel common power format (CPF) flow. The test-chip will be fabricated in the TSMC 90 nm CMOS technology, of which the estimated power dissipations are 156.62 mW for 350 MHz @1 V and 46.60 mW for 230 MHz @0.7 V respectively.
DOI:10.1109/SOCDC.2008.4815620