High-speed performance of 0.35 μm CMOS gates fabricated on low-dose SIMOX substrates with/without an N-well underneath the buried oxide layer

We present experimental results concerning the propagation delay time of the 0.35 μm CMOS gate chains (inverter, 3NAND, and 3NOR) fabricated on low-dose SIMOX substrates with and without the N-well formed underneath the buried oxide layer in the PMOS region. Using such experimental data as the capac...

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Bibliographic Details
Published in:IEEE electron device letters 1996-03, Vol.17 (3), p.106-108
Main Authors: Yoshino, A., Kumagai, K., Hamatake, N., Tatsumi, T., Onishi, H., Kurosawa, S., Okumura, K.
Format: Article
Language:English
Subjects:
Capacitance measurement
Capacitance-voltage characteristics
Circuits
Laboratories
MOSFETs
Parasitic capacitance
Propagation delay
Silicon
Substrates
Time measurement
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Summary:We present experimental results concerning the propagation delay time of the 0.35 μm CMOS gate chains (inverter, 3NAND, and 3NOR) fabricated on low-dose SIMOX substrates with and without the N-well formed underneath the buried oxide layer in the PMOS region. Using such experimental data as the capacitance voltage characteristics of the buried oxide layer, and the enhanced PMOS transistor drivability due to the negative back bias effect, we clarify the most essential factor of the high-speed performance of the CMOS/SIMOX circuits fabricated on a low-dose SIMOX substrate.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.485182