A model of VHDL for the analysis, transformation, and optimization of digital system designs

Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses well-formedness, static equivalences, and static r...

Full description

Saved in:
Bibliographic Details
Main Authors: Wilsey, P.A., Benz, D.M., Pandey, S.L.
Format: Conference Proceeding
Language:English
Subjects:
Algebra
Buildings
Computer architecture
Costs
Design automation
Design optimization
Digital systems
Handicapped aids
Hardware design languages
Libraries
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses well-formedness, static equivalences, and static rewriting is presented. A rewriting algebra is presented that defines a set of transforms that allow the rewriting of VHDL descriptions into a reduced form. The dynamic semantics is under development and the reductions attained by the rewriting algebra have greatly simplified the language constructs that the dynamic semantics have to characterize.
DOI:10.1109/ASPDAC.1995.486377