Circuit techniques for 10 and 20 Gb/s clock recovery using a fully balanced narrowband regenerative frequency divider with 0.3 /spl mu/m HEMTs [SDH/SONET]

The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes. At 10 Gb/s input data, the tank circuit of the preprocessor r...

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Bibliographic Details
Main Authors: Zhi-Gong Wang, Berroth, M., Thiede, A., Rieger-Motzer, M., Hofmann, P., Hulsmann, A., Kohler, K., Raynor, B., Schneider, J., Briggmann, D.
Format: Conference Proceeding
Language:English
Subjects:
Chromium
Clocks
Filters
Frequency conversion
HEMTs
Inductors
MODFETs
Monolithic integrated circuits
Narrowband
Phase locked loops
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Description
Summary:The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes. At 10 Gb/s input data, the tank circuit of the preprocessor resonates at the second harmonic of the clock frequency. This mode can be used for 10 Gb/s direct data decision. At 20 Gb/s the tank circuit resonates at the fundamental frequency of the clock signal. This mode is optimal for a 20 Gb/s parallel data decision.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.1996.488572