Implementation of synthesized digital systems with VHDL

This paper presents a software system for implementing synthesized digital designs using VHDL so that the designs can be accepted by existing CAD systems to achieve low-level verification such as delay analysis and logic simulation as well as layout realization in various technologies.

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Bibliographic Details
Main Authors: Ng, L.S., Jong, C.C.
Format: Conference Proceeding
Language:English
Subjects:
Analytical models
Control system synthesis
Delay
Design automation
Digital systems
Flow graphs
Hardware design languages
High level synthesis
Logic design
Software systems
Online Access:Request full text
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Description
Summary:This paper presents a software system for implementing synthesized digital designs using VHDL so that the designs can be accepted by existing CAD systems to achieve low-level verification such as delay analysis and logic simulation as well as layout realization in various technologies.
DOI:10.1109/TENCON.1995.496409