A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications

The proposed MVC encoder chip is characterized as follows: 1) View-parallel MB-interleaved (VPMBI) scheduling with 8-stage MB pipelining is introduced to overcome the first 2 challenges. With this technique, the processing capability is 212 Mpixels/s, at least 3.4times better than the previous works...

Full description

Saved in:
Bibliographic Details
Main Authors: Li-Fu Ding, Wei-Yin Chen, Pei-Kuei Tsung, Tzu-Der Chuang, Hsu-Kuang Chiu, Yu-Han Chen, Pai-Heng Hsiao, Shao-Yi Chien, Tung-Chien Chen, Ping-Chih Lin, Chia-Yu Chang, Liang-Gee Chen
Format: Conference Proceeding
Language:English
Subjects:
Automatic voltage control
Bandwidth
Computer architecture
Filters
HDTV
Pipeline processing
Prefetching
Random access memory
Scalability
Throughput
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The proposed MVC encoder chip is characterized as follows: 1) View-parallel MB-interleaved (VPMBI) scheduling with 8-stage MB pipelining is introduced to overcome the first 2 challenges. With this technique, the processing capability is 212 Mpixels/s, at least 3.4times better than the previous works. In addition, view scalability is achieved and supports real-time processing from single-view 4096times2160p to 7-view 720p videos. 2) The cache-based prediction core with a search window (SW) prefetching scheme and a predictor-centered ME/DE algorithm effectively reduces 83% on-chip memory size and 39% external memory bandwidth compared. These techniques enable the design of H.264/AVC Multiview Extension and High Profile encoder. The core size of the chip is 11.46 mm 2 , which contains 1732 K gates using 90 nm CMOS technology. The This chip supports a maximum throughput of 830 kMB/s at 280 MHz for 4096times2160p videos.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2009.4977354