A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

Today NAND flash memory is used for data and code storage in digital cameras, USB devices, cell phones, camcorders, and solid-state disk drives. To satisfy the market demand for lower cost per bit and higher density nonvolatile memory, in addition to technology scaling, 2 b/cell MLC technology was i...

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Main Authors: Trinh, C., Shibata, N., Nakano, T., Ogawa, M., Sato, J., Takeyama, Y., Isobe, K., Le, B., Moogat, F., Mokhlesi, N., Kozakai, K., Hong, P., Kamei, T., Iwasa, K., Nakai, J., Shimizu, T., Honma, M., Sakai, S., Kawaai, T., Hoshi, S., Yuh, J., Hsu, C., Tseng, T., Li, J., Hu, J., Liu, M., Khalid, S., Chen, J., Watanabe, M., Lin, H., Yang, J., McKay, K., Nguyen, K., Pham, T., Matsuda, Y., Nakamura, K., Kanebako, K., Yoshikawa, S., Igarashi, W., Inoue, A., Takahashi, T., Komatsu, Y., Suzuki, C., Kanazawa, K., Higashitani, M., Lee, S., Murai, T., Lan, J., Huynh, S., Murin, M., Shlick, M., Lasser, M., Cernea, R., Mofidi, M., Schuegraf, K., Quader, K.
Format: Conference Proceeding
Language:English
Subjects:
Circuit testing
CMOS technology
Flash memory
Joining processes
Noise level
Noise reduction
Threshold voltage
Throughput
Very large scale integration
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creator Trinh, C.
Shibata, N.
Nakano, T.
Ogawa, M.
Sato, J.
Takeyama, Y.
Isobe, K.
Le, B.
Moogat, F.
Mokhlesi, N.
Kozakai, K.
Hong, P.
Kamei, T.
Iwasa, K.
Nakai, J.
Shimizu, T.
Honma, M.
Sakai, S.
Kawaai, T.
Hoshi, S.
Yuh, J.
Hsu, C.
Tseng, T.
Li, J.
Hu, J.
Liu, M.
Khalid, S.
Chen, J.
Watanabe, M.
Lin, H.
Yang, J.
McKay, K.
Nguyen, K.
Pham, T.
Matsuda, Y.
Nakamura, K.
Kanebako, K.
Yoshikawa, S.
Igarashi, W.
Inoue, A.
Takahashi, T.
Komatsu, Y.
Suzuki, C.
Kanazawa, K.
Higashitani, M.
Lee, S.
Murai, T.
Lan, J.
Huynh, S.
Murin, M.
Shlick, M.
Lasser, M.
Cernea, R.
Mofidi, M.
Schuegraf, K.
Quader, K.
description Today NAND flash memory is used for data and code storage in digital cameras, USB devices, cell phones, camcorders, and solid-state disk drives. To satisfy the market demand for lower cost per bit and higher density nonvolatile memory, in addition to technology scaling, 2 b/cell MLC technology was introduced. Recently MLC NAND flash memories with more than 2 b/cell have been reported. To meet market demands we develop a 5.6 Mb/s 64 Gb 4 b/cell NAND flash memory in 43 nm CMOS. At 5.6 Mb/s, it is suitable for many mainstream applications. The chip has two 32 Gb memory arrays. One NAND string is composed of 66 NAND cells (64 + 2 dummies). With 64 wordlines (WL) per block, 4 pages per WL (4 b/cell), and an 8 KB page size, with block size of 2 MB. The performance is improved with page size extended to 8 KB, by programming 8 KB x 4 b/cell x 2 planes at the same time.
doi_str_mv 10.1109/ISSCC.2009.4977400
format conference_proceeding
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To satisfy the market demand for lower cost per bit and higher density nonvolatile memory, in addition to technology scaling, 2 b/cell MLC technology was introduced. Recently MLC NAND flash memories with more than 2 b/cell have been reported. To meet market demands we develop a 5.6 Mb/s 64 Gb 4 b/cell NAND flash memory in 43 nm CMOS. At 5.6 Mb/s, it is suitable for many mainstream applications. The chip has two 32 Gb memory arrays. One NAND string is composed of 66 NAND cells (64 + 2 dummies). With 64 wordlines (WL) per block, 4 pages per WL (4 b/cell), and an 8 KB page size, with block size of 2 MB. The performance is improved with page size extended to 8 KB, by programming 8 KB x 4 b/cell x 2 planes at the same time.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.2009.4977400</doi></addata></record>
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identifier ISSN: 0193-6530
ispartof 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.246-247,247a
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2376-8606
language eng
recordid cdi_ieee_primary_4977400
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Circuit testing
CMOS technology
Flash memory
Joining processes
Noise level
Noise reduction
Threshold voltage
Throughput
Very large scale integration
title A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS
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