A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes

• Main Authors: Shiga, H., Takashima, D., Shiratake, S., Hoya, K., Miyakawa, T., Ogiwara, R., Fukuda, R., Takizawa, R., Hatsuda, K., Matsuoka, F., Nagadomi, Y., Hashimoto, D., Nishimura, H., Hioka, T., Doumae, S., Shimizu, S., Kawano, M., Taguchi, T., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Kumura, Y., Shimojo, Y., Yamada, Y., Minami, Y., Shuto, S., Yamakawa, K., Yamazaki, S., Kunishima, I., Hamamoto, T., Nitayama, A., Furuyama, T.
• Format: Conference Proceeding
• Language: English
• Subjects: Application software; Bandwidth; Cellular phones; Ferroelectric films; Mobile computing; Nonvolatile memory; Personal communication networks; Random access memory; Read-write memory; System performance
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2009.4977509

An application that takes advantage of FeRAM characteristics is replacing current DRAM, which then becomes high-performance nonvolatile RAM cache. This improves system performance for many kinds of computer systems, including mobile PCs, cellular phones, digital video products, and storage systems such as SSDs. However, the highest capacity in nonvolatile RAMs that allow frequent cache reads and writes is limited to 64 Mb. The maximum read bandwidth is limited to 400 Mb/s and the write bandwidth is limited to 200 Mb/s in nonvolatile memories reported to date. The FeRAm was demonstrated in 4M 0.13 mum CMOS. A serious problem with FeRAM scaling is cell-signal degradation due to ferroelectric capacitor scaling. The circuit diagram and device feature are also summarizes.