A VLSI implementation of multi-layer neural network with ternary activation functions and limited integer weights

This paper describes a digital neural network architecture and its VLSI implementation. Multi-layer neural networks are made feasible through input and output signal multiplexing, ternary quantisation of signals and integer weights. Use of the chip is demonstrated in the simulation of a character re...

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Bibliographic Details
Main Authors: Hoskins, B.G., Haskard, M.R., Curkowicz, G.R.
Format: Conference Proceeding
Language:English
Subjects:
Application software
Artificial neural networks
Character recognition
Floating-point arithmetic
Hardware
Intelligent networks
Multi-layer neural network
Neural networks
Quantization
Very large scale integration
Online Access:Request full text
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Summary:This paper describes a digital neural network architecture and its VLSI implementation. Multi-layer neural networks are made feasible through input and output signal multiplexing, ternary quantisation of signals and integer weights. Use of the chip is demonstrated in the simulation of a character recognition problem.
DOI:10.1109/ICMEL.1995.500978