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Chip-packaging interaction in Cu/very low-k interconnect
Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a pa...
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Main Authors: | , , , , , |
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Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Citations: | Items that cite this one |
Online Access: | Request full text |
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Summary: | Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a packaging reliability point of view. Factors including top metal (or SiO 2 ) thickness, passivation dielectric layers, and bump pad structure are found to play key roles in packaging process and reliability. |
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ISSN: | 2380-632X 2380-6338 |
DOI: | 10.1109/IITC.2009.5090366 |