A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors

This paper deals with a methodology for software estimation to enable design space exploration of heterogeneous multiprocessor systems. Starting from fork-join representation of application specification along with high level description of multiprocessor target architecture and mapping of applicati...

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Bibliographic Details
Main Authors: Sahu, A., Balakrishnan, M., Panda, P.R.
Format: Conference Proceeding
Language:English
Subjects:
Application software
Computer architecture
Computer science
Delay estimation
Design engineering
Optimizing compilers
Paper technology
Software performance
Space exploration
Space technology
Online Access:Request full text
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Summary:This paper deals with a methodology for software estimation to enable design space exploration of heterogeneous multiprocessor systems. Starting from fork-join representation of application specification along with high level description of multiprocessor target architecture and mapping of application components onto architecture resource elements, it estimates the performance of application on target multiprocessor architecture. The methodology proposed includes the effect of basic compiler optimizations, integrates light weight memory simulation and instruction mapping for complex instruction to improve the accuracy of software estimation. To estimate performance degradation due to contention for shared resources like memory and bus, synthetic access traces coupled with interval analysis technique is employed. The methodology has been validated on a real heterogeneous platform. Results show that using estimation it is possible to predict performance with average errors of around 11%.
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2009.5090813