Test exploration and validation using transaction level models

The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space exploration and validation of test strategies and schedules using transaction level models (TLMs). Since many aspects of te...

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Bibliographic Details
Main Authors: Kochte, M.A., Zoellin, C.G., Imhof, M.E., Khaligh, R.S., Radetzki, M., Wunderlich, H.-J., Di Carlo, S., Prinetto, P.
Format: Conference Proceeding
Language:English
Subjects:
Automatic testing
Computational modeling
Concurrent computing
Context modeling
Design for testability
design-for-test
Discrete event simulation
Object oriented modeling
Scheduling
Space exploration
System testing
Test of systems-on-chip
transaction level modeling
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Summary:The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space exploration and validation of test strategies and schedules using transaction level models (TLMs). Since many aspects of testing involve the transfer of a significant amount of test stimuli and responses, the communication-centric view of TLMs suits this purpose exceptionally well.
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2009.5090856