A very high performance and manufacturable 3.3 V 0.35-/spl mu/m CMOS technology for ASICs

In this paper a manufacturable and high performance 0.35 /spl mu/m CMOS ASIC technology optimized for 3.3 V operation is presented. This CMOS technology features a 65 /spl Aring/ gate oxide, single n/sup +/-polysilicon gate, and 3 levels of metal. An improvement of 1.6X in circuit performance and 1....

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Main Authors: Kizilyalli, I.C., Lytle, S.A., Jones, B.R., Martin, E.P., Shive, S.F., Brooks, A.L., Thoma, M.J., Schanzer, R.W., Sniegowski, J.W., Wroge, D.M., Key, R.W., Kearney, J.W., Stiles, K.R.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
CMOS process
CMOS technology
Delay effects
Etching
Implants
Manufacturing
MOS devices
MOSFETs
Ring oscillators
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Summary:In this paper a manufacturable and high performance 0.35 /spl mu/m CMOS ASIC technology optimized for 3.3 V operation is presented. This CMOS technology features a 65 /spl Aring/ gate oxide, single n/sup +/-polysilicon gate, and 3 levels of metal. An improvement of 1.6X in circuit performance and 1.56X in packing density is achieved over AT&T's previous generation 0.5 /spl mu/m 3.3 volt CMOS technology by device scaling, and aggressive isolation and interconnect design rules. The nominal ring oscillator delay time is 50 ps.
DOI:10.1109/CICC.1996.510506