Restrict Encoding for Mixed-Mode BIST

Programmable mixed-mode BIST schemes combine pseudo-random pattern testing and deterministic test. This paper presents a synthesis technique for a mixed-mode BIST scheme which is able to exploit the regularities of a deterministic test pattern set for minimizing the hardware overhead and memory requ...

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Bibliographic Details
Main Authors: Hakmi, A.-W., Holst, S., Wunderlich, H.-J., Schloffel, J., Hapke, F., Glowatz, A.
Format: Conference Proceeding
Language:English
Subjects:
Built-in self-test
Circuit faults
Circuit testing
Clocks
Costs
Deterministic BIST
Dictionaries
Encoding
Hardware
Shift registers
Very large scale integration
Online Access:Request full text
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Description
Summary:Programmable mixed-mode BIST schemes combine pseudo-random pattern testing and deterministic test. This paper presents a synthesis technique for a mixed-mode BIST scheme which is able to exploit the regularities of a deterministic test pattern set for minimizing the hardware overhead and memory requirements. The scheme saves more than 50% hardware costs compared with the best schemes known so far while complete programmability is still preserved.
ISSN:1093-0167
2375-1053
DOI:10.1109/VTS.2009.43