Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection

With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be signifi...

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Bibliographic Details
Main Authors: Wen-Yi Chen, Ming-Dou Ker, Yeh-Ning Jou, Yeh-Jen Huang, Geeng-Lih Lin
Format: Conference Proceeding
Language:English
Subjects:
CMOS technology
Current measurement
Electrostatic discharge
Integrated circuit modeling
Laboratories
Nanoelectronics
Protection
Robustness
Trigger circuits
Voltage
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Summary:With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2009.5117766