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Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection
With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be signifi...
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creator | Wen-Yi Chen Ming-Dou Ker Yeh-Ning Jou Yeh-Jen Huang Geeng-Lih Lin |
description | With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs. |
doi_str_mv | 10.1109/ISCAS.2009.5117766 |
format | conference_proceeding |
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The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2009.5117766</doi><tpages>4</tpages></addata></record> |
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ispartof | 2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.385-388 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | CMOS technology Current measurement Electrostatic discharge Integrated circuit modeling Laboratories Nanoelectronics Protection Robustness Trigger circuits Voltage |
title | Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection |
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