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Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection

With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be signifi...

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Main Authors: Wen-Yi Chen, Ming-Dou Ker, Yeh-Ning Jou, Yeh-Jen Huang, Geeng-Lih Lin
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Ming-Dou Ker
Yeh-Ning Jou
Yeh-Jen Huang
Geeng-Lih Lin
description With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.
doi_str_mv 10.1109/ISCAS.2009.5117766
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5117766</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5117766</ieee_id><sourcerecordid>5117766</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-9f7ba13f14849afec2437f74f72774fdfca9c66fde358623197dbbbd34f8ba5f3</originalsourceid><addsrcrecordid>eNpFkEtuwjAARN0PUgPtBdqNLxDqv5MlCrSNRMUi7ZraiQ1GIUZ2QMrtCypSNzPSPOktBoBnjKYYo_y1rIpZNSUI5VOOsZRC3IAxZoQxmpGM3YKEYJ6lmBN-9w-kuAcJIhKnjCIyAkmGUsEEp-gBjGPcIXQ2CpKAn3J_CP5k9qbroe_goprD4PUx9p2JEXoLW9WboFo4_1xV0HVw6zbb9OTbXm0MLC5jWUSoB6h9M8D6GMJF5bqdqXvnu0cwsqqN5unaE_D9tvgqPtLl6r0sZsvUYcn7NLdSK0wtZhnLlTU1YVRayawk8pyNrVVeC2EbQ3kmCMW5bLTWDWU204pbOgEvf15njFkfgturMKyvl9FfjYVaNw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Wen-Yi Chen ; Ming-Dou Ker ; Yeh-Ning Jou ; Yeh-Jen Huang ; Geeng-Lih Lin</creator><creatorcontrib>Wen-Yi Chen ; Ming-Dou Ker ; Yeh-Ning Jou ; Yeh-Jen Huang ; Geeng-Lih Lin</creatorcontrib><description>With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 1424438276</identifier><identifier>ISBN: 9781424438273</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 1424438284</identifier><identifier>EISBN: 9781424438280</identifier><identifier>DOI: 10.1109/ISCAS.2009.5117766</identifier><identifier>LCCN: 80-646530</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS technology ; Current measurement ; Electrostatic discharge ; Integrated circuit modeling ; Laboratories ; Nanoelectronics ; Protection ; Robustness ; Trigger circuits ; Voltage</subject><ispartof>2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.385-388</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5117766$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5117766$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Wen-Yi Chen</creatorcontrib><creatorcontrib>Ming-Dou Ker</creatorcontrib><creatorcontrib>Yeh-Ning Jou</creatorcontrib><creatorcontrib>Yeh-Jen Huang</creatorcontrib><creatorcontrib>Geeng-Lih Lin</creatorcontrib><title>Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection</title><title>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.</description><subject>CMOS technology</subject><subject>Current measurement</subject><subject>Electrostatic discharge</subject><subject>Integrated circuit modeling</subject><subject>Laboratories</subject><subject>Nanoelectronics</subject><subject>Protection</subject><subject>Robustness</subject><subject>Trigger circuits</subject><subject>Voltage</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>1424438276</isbn><isbn>9781424438273</isbn><isbn>1424438284</isbn><isbn>9781424438280</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpFkEtuwjAARN0PUgPtBdqNLxDqv5MlCrSNRMUi7ZraiQ1GIUZ2QMrtCypSNzPSPOktBoBnjKYYo_y1rIpZNSUI5VOOsZRC3IAxZoQxmpGM3YKEYJ6lmBN-9w-kuAcJIhKnjCIyAkmGUsEEp-gBjGPcIXQ2CpKAn3J_CP5k9qbroe_goprD4PUx9p2JEXoLW9WboFo4_1xV0HVw6zbb9OTbXm0MLC5jWUSoB6h9M8D6GMJF5bqdqXvnu0cwsqqN5unaE_D9tvgqPtLl6r0sZsvUYcn7NLdSK0wtZhnLlTU1YVRayawk8pyNrVVeC2EbQ3kmCMW5bLTWDWU204pbOgEvf15njFkfgturMKyvl9FfjYVaNw</recordid><startdate>200905</startdate><enddate>200905</enddate><creator>Wen-Yi Chen</creator><creator>Ming-Dou Ker</creator><creator>Yeh-Ning Jou</creator><creator>Yeh-Jen Huang</creator><creator>Geeng-Lih Lin</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200905</creationdate><title>Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection</title><author>Wen-Yi Chen ; Ming-Dou Ker ; Yeh-Ning Jou ; Yeh-Jen Huang ; Geeng-Lih Lin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-9f7ba13f14849afec2437f74f72774fdfca9c66fde358623197dbbbd34f8ba5f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>CMOS technology</topic><topic>Current measurement</topic><topic>Electrostatic discharge</topic><topic>Integrated circuit modeling</topic><topic>Laboratories</topic><topic>Nanoelectronics</topic><topic>Protection</topic><topic>Robustness</topic><topic>Trigger circuits</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Wen-Yi Chen</creatorcontrib><creatorcontrib>Ming-Dou Ker</creatorcontrib><creatorcontrib>Yeh-Ning Jou</creatorcontrib><creatorcontrib>Yeh-Jen Huang</creatorcontrib><creatorcontrib>Geeng-Lih Lin</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore (Online service)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wen-Yi Chen</au><au>Ming-Dou Ker</au><au>Yeh-Ning Jou</au><au>Yeh-Jen Huang</au><au>Geeng-Lih Lin</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection</atitle><btitle>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2009-05</date><risdate>2009</risdate><spage>385</spage><epage>388</epage><pages>385-388</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>1424438276</isbn><isbn>9781424438273</isbn><eisbn>1424438284</eisbn><eisbn>9781424438280</eisbn><abstract>With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mum 16-V BCD process. The TLP measured results confirmed that the secondary breakdown current (I t2 ) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2009.5117766</doi><tpages>4</tpages></addata></record>
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subjects CMOS technology
Current measurement
Electrostatic discharge
Integrated circuit modeling
Laboratories
Nanoelectronics
Protection
Robustness
Trigger circuits
Voltage
title Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T14%3A24%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Improvement%20on%20ESD%20robustness%20of%20lateral%20DMOS%20in%20high-voltage%20CMOS%20ICs%20by%20body%20current%20injection&rft.btitle=2009%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Wen-Yi%20Chen&rft.date=2009-05&rft.spage=385&rft.epage=388&rft.pages=385-388&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=1424438276&rft.isbn_list=9781424438273&rft_id=info:doi/10.1109/ISCAS.2009.5117766&rft.eisbn=1424438284&rft.eisbn_list=9781424438280&rft_dat=%3Cieee_6IE%3E5117766%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-9f7ba13f14849afec2437f74f72774fdfca9c66fde358623197dbbbd34f8ba5f3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5117766&rfr_iscdi=true