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AATMA: an algorithm for technology mapping for antifuse-based FPGAs
The paper presents AATMA: a technology mapping algorithm for antifuse based FPGAs. The algorithm is independent of the logic module structure. It can handle large libraries with complex functions and uses a signature-matching based approach to achieve high mapping quality and shorter execution times...
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creator | Mehendale, M. Ram Prasad, M.K. |
description | The paper presents AATMA: a technology mapping algorithm for antifuse based FPGAs. The algorithm is independent of the logic module structure. It can handle large libraries with complex functions and uses a signature-matching based approach to achieve high mapping quality and shorter execution times. This makes it a powerful tool not only for mapping designs onto a logic module but also for the design and evaluation of antifuse-based FPGA logic module architectures. The details of the overall algorithm along with the signature matching technique are presented. The experimental results show that AATMA needs upto 15-20% fewer logic modules than MISII and is upto 15 to 20 times faster. |
doi_str_mv | 10.1109/ICVD.1995.512080 |
format | conference_proceeding |
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The algorithm is independent of the logic module structure. It can handle large libraries with complex functions and uses a signature-matching based approach to achieve high mapping quality and shorter execution times. This makes it a powerful tool not only for mapping designs onto a logic module but also for the design and evaluation of antifuse-based FPGA logic module architectures. The details of the overall algorithm along with the signature matching technique are presented. The experimental results show that AATMA needs upto 15-20% fewer logic modules than MISII and is upto 15 to 20 times faster.</description><identifier>ISSN: 1063-9667</identifier><identifier>ISBN: 9780818669057</identifier><identifier>ISBN: 0818669055</identifier><identifier>EISSN: 2380-6923</identifier><identifier>DOI: 10.1109/ICVD.1995.512080</identifier><language>eng</language><publisher>IEEE</publisher><subject>Automation ; Field programmable gate arrays ; Instruments ; Libraries ; Logic design ; Logic programming ; Paper technology ; Programmable logic arrays ; Routing ; Silicon</subject><ispartof>Proceedings of the 8th International Conference on VLSI Design, 1995, p.69-74</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/512080$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,4047,4048,27923,54553,54918,54930</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/512080$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Mehendale, M.</creatorcontrib><creatorcontrib>Ram Prasad, M.K.</creatorcontrib><title>AATMA: an algorithm for technology mapping for antifuse-based FPGAs</title><title>Proceedings of the 8th International Conference on VLSI Design</title><addtitle>ICVD</addtitle><description>The paper presents AATMA: a technology mapping algorithm for antifuse based FPGAs. The algorithm is independent of the logic module structure. It can handle large libraries with complex functions and uses a signature-matching based approach to achieve high mapping quality and shorter execution times. This makes it a powerful tool not only for mapping designs onto a logic module but also for the design and evaluation of antifuse-based FPGA logic module architectures. The details of the overall algorithm along with the signature matching technique are presented. The experimental results show that AATMA needs upto 15-20% fewer logic modules than MISII and is upto 15 to 20 times faster.</description><subject>Automation</subject><subject>Field programmable gate arrays</subject><subject>Instruments</subject><subject>Libraries</subject><subject>Logic design</subject><subject>Logic programming</subject><subject>Paper technology</subject><subject>Programmable logic arrays</subject><subject>Routing</subject><subject>Silicon</subject><issn>1063-9667</issn><issn>2380-6923</issn><isbn>9780818669057</isbn><isbn>0818669055</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1995</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNp9jrsOgjAUQG98JOJjN079AfAWQmndCD4HEwfiSqoWrIFCKA7-vYk6O53knOUAzCl6lKJYHpLz2qNChF5IfeTYA8cPOLpM-EEfZiLiyClnTGAYDcChyAJXMBaNYGztAxF5iJEDSRynx3hFpCGyLOpWd_eK5HVLOnW9m7qsixepZNNoU3y0NJ3On1a5F2nVjWxPu9hOYZjL0qrZjxNYbDdpsne1UiprWl3J9pV9N4O_8Q2XSDvy</recordid><startdate>1995</startdate><enddate>1995</enddate><creator>Mehendale, M.</creator><creator>Ram Prasad, M.K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1995</creationdate><title>AATMA: an algorithm for technology mapping for antifuse-based FPGAs</title><author>Mehendale, M. ; Ram Prasad, M.K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_5120803</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Automation</topic><topic>Field programmable gate arrays</topic><topic>Instruments</topic><topic>Libraries</topic><topic>Logic design</topic><topic>Logic programming</topic><topic>Paper technology</topic><topic>Programmable logic arrays</topic><topic>Routing</topic><topic>Silicon</topic><toplevel>online_resources</toplevel><creatorcontrib>Mehendale, M.</creatorcontrib><creatorcontrib>Ram Prasad, M.K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore Digital Library</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mehendale, M.</au><au>Ram Prasad, M.K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>AATMA: an algorithm for technology mapping for antifuse-based FPGAs</atitle><btitle>Proceedings of the 8th International Conference on VLSI Design</btitle><stitle>ICVD</stitle><date>1995</date><risdate>1995</risdate><spage>69</spage><epage>74</epage><pages>69-74</pages><issn>1063-9667</issn><eissn>2380-6923</eissn><isbn>9780818669057</isbn><isbn>0818669055</isbn><abstract>The paper presents AATMA: a technology mapping algorithm for antifuse based FPGAs. The algorithm is independent of the logic module structure. It can handle large libraries with complex functions and uses a signature-matching based approach to achieve high mapping quality and shorter execution times. This makes it a powerful tool not only for mapping designs onto a logic module but also for the design and evaluation of antifuse-based FPGA logic module architectures. The details of the overall algorithm along with the signature matching technique are presented. The experimental results show that AATMA needs upto 15-20% fewer logic modules than MISII and is upto 15 to 20 times faster.</abstract><pub>IEEE</pub><doi>10.1109/ICVD.1995.512080</doi></addata></record> |
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ispartof | Proceedings of the 8th International Conference on VLSI Design, 1995, p.69-74 |
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source | IEEE Xplore All Conference Series |
subjects | Automation Field programmable gate arrays Instruments Libraries Logic design Logic programming Paper technology Programmable logic arrays Routing Silicon |
title | AATMA: an algorithm for technology mapping for antifuse-based FPGAs |
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