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Effect of device layout on the thermal resistance of high-power thermally-shunted heterojunction bipolar transistors
The effect of device layout on thermal impedance of thermally-shunted HBTs was investigated. A direct comparison of thermally shunted devices and standard airbridge devices is made. Changes in thermal resistance of up to 67% were observed. While thermal resistance remains sensitive to emitter elemen...
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| container_end_page | 1610 vol.3 |
| container_issue | |
| container_start_page | 1607 |
| container_title | |
| container_volume | 3 |
| creator | Dettmer, R. Jenkins, T. Barrette, J. Bozada, C. Desalvo, G. Ebel, J. Gillespie, J. Havasy, C. Ito, C. Nakano, K. Pettiford, C. Quach, T. Sewell, J. Via, D. Anholt, R. |
| description | The effect of device layout on thermal impedance of thermally-shunted HBTs was investigated. A direct comparison of thermally shunted devices and standard airbridge devices is made. Changes in thermal resistance of up to 67% were observed. While thermal resistance remains sensitive to emitter element placement in thermally shunted devices, variations in the location of thermal shunt landings had little effect. These results provide a basis for optimizing thermally-shunted devices. |
| doi_str_mv | 10.1109/MWSYM.1996.512245 |
| format | conference_proceeding |
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A direct comparison of thermally shunted devices and standard airbridge devices is made. Changes in thermal resistance of up to 67% were observed. While thermal resistance remains sensitive to emitter element placement in thermally shunted devices, variations in the location of thermal shunt landings had little effect. These results provide a basis for optimizing thermally-shunted devices.</description><subject>Current distribution</subject><subject>Fingers</subject><subject>Heat sinks</subject><subject>Heterojunction bipolar transistors</subject><subject>Impedance</subject><subject>Laboratories</subject><subject>Temperature</subject><subject>Thermal force</subject><subject>Thermal management</subject><subject>Thermal resistance</subject><issn>0149-645X</issn><issn>2576-7216</issn><isbn>0780332466</isbn><isbn>9780780332461</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1996</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1kM1KAzEUhYM_YK19AF3NC6QmmdxkspRSf6DFhYq6KpnOjZMynSlJqszbO6V64XDg8PEtLiHXnE05Z-Z2-f7yuZxyY9QUuBASTshIgFZUC65OySXTBctzIZU6IyPGpaFKwscFmcS4YcNJAAFmRNLcOVynrHNZhd9-jVlj-24_DG2WajwkbG2TBYw-JtsOwIDW_qumu-4Hwz_Q9DTW-zZhldWYMHSbfbtOfrCUftc1dgCDbQ-OLsQrcu5sE3Hy12Pydj9_nT3SxfPD0-xuQT3XIlFXidzmCLp0gM4w5YS0YC2A5aoopUYHhguskBnmGBpbFNJVunASSkCVj8nN0esRcbULfmtDvzr-K_8F-AVgyQ</recordid><startdate>1996</startdate><enddate>1996</enddate><creator>Dettmer, R.</creator><creator>Jenkins, T.</creator><creator>Barrette, J.</creator><creator>Bozada, C.</creator><creator>Desalvo, G.</creator><creator>Ebel, J.</creator><creator>Gillespie, J.</creator><creator>Havasy, C.</creator><creator>Ito, C.</creator><creator>Nakano, K.</creator><creator>Pettiford, C.</creator><creator>Quach, T.</creator><creator>Sewell, J.</creator><creator>Via, D.</creator><creator>Anholt, R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1996</creationdate><title>Effect of device layout on the thermal resistance of high-power thermally-shunted heterojunction bipolar transistors</title><author>Dettmer, R. ; Jenkins, T. ; Barrette, J. ; Bozada, C. ; Desalvo, G. ; Ebel, J. ; Gillespie, J. ; Havasy, C. ; Ito, C. ; Nakano, K. ; Pettiford, C. ; Quach, T. ; Sewell, J. ; Via, D. ; Anholt, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-fd23a3e57bf5ef906f24a5aa55a168b47ef5912ede090f0e9a884fd78f45b5e63</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Current distribution</topic><topic>Fingers</topic><topic>Heat sinks</topic><topic>Heterojunction bipolar transistors</topic><topic>Impedance</topic><topic>Laboratories</topic><topic>Temperature</topic><topic>Thermal force</topic><topic>Thermal management</topic><topic>Thermal resistance</topic><toplevel>online_resources</toplevel><creatorcontrib>Dettmer, R.</creatorcontrib><creatorcontrib>Jenkins, T.</creatorcontrib><creatorcontrib>Barrette, J.</creatorcontrib><creatorcontrib>Bozada, C.</creatorcontrib><creatorcontrib>Desalvo, G.</creatorcontrib><creatorcontrib>Ebel, J.</creatorcontrib><creatorcontrib>Gillespie, J.</creatorcontrib><creatorcontrib>Havasy, C.</creatorcontrib><creatorcontrib>Ito, C.</creatorcontrib><creatorcontrib>Nakano, K.</creatorcontrib><creatorcontrib>Pettiford, C.</creatorcontrib><creatorcontrib>Quach, T.</creatorcontrib><creatorcontrib>Sewell, J.</creatorcontrib><creatorcontrib>Via, D.</creatorcontrib><creatorcontrib>Anholt, R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dettmer, R.</au><au>Jenkins, T.</au><au>Barrette, J.</au><au>Bozada, C.</au><au>Desalvo, G.</au><au>Ebel, J.</au><au>Gillespie, J.</au><au>Havasy, C.</au><au>Ito, C.</au><au>Nakano, K.</au><au>Pettiford, C.</au><au>Quach, T.</au><au>Sewell, J.</au><au>Via, D.</au><au>Anholt, R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Effect of device layout on the thermal resistance of high-power thermally-shunted heterojunction bipolar transistors</atitle><btitle>1996 IEEE MTT-S International Microwave Symposium Digest</btitle><stitle>MWSYM</stitle><date>1996</date><risdate>1996</risdate><volume>3</volume><spage>1607</spage><epage>1610 vol.3</epage><pages>1607-1610 vol.3</pages><issn>0149-645X</issn><eissn>2576-7216</eissn><isbn>0780332466</isbn><isbn>9780780332461</isbn><abstract>The effect of device layout on thermal impedance of thermally-shunted HBTs was investigated. A direct comparison of thermally shunted devices and standard airbridge devices is made. Changes in thermal resistance of up to 67% were observed. While thermal resistance remains sensitive to emitter element placement in thermally shunted devices, variations in the location of thermal shunt landings had little effect. These results provide a basis for optimizing thermally-shunted devices.</abstract><pub>IEEE</pub><doi>10.1109/MWSYM.1996.512245</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0149-645X |
| ispartof | 1996 IEEE MTT-S International Microwave Symposium Digest, 1996, Vol.3, p.1607-1610 vol.3 |
| issn | 0149-645X 2576-7216 |
| language | eng |
| recordid | cdi_ieee_primary_512245 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Current distribution Fingers Heat sinks Heterojunction bipolar transistors Impedance Laboratories Temperature Thermal force Thermal management Thermal resistance |
| title | Effect of device layout on the thermal resistance of high-power thermally-shunted heterojunction bipolar transistors |
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