Microarchitecture of HaL's memory management unit

This paper discusses the architecture and implementation of HaL's 64-bit memory management unit (MMU). The MMU is responsible for virtual-to-physical address translations, data movement controls, bus interfaces among CPU/caches, memory subsystems; and I/O systems; and maintaining memory coheren...

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Bibliographic Details
Main Authors: Chang, D.C.-W., Lyon, D., Chen, C., Peng, L., Massoumi, M., Hakimi, M., Iyengar, S., Li, E., Remedios, R.
Format: Conference Proceeding
Language:English
Subjects:
Control systems
Data structures
Delay
Hardware
Legged locomotion
Memory management
Microarchitecture
Physics computing
Pipelines
Registers
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Summary:This paper discusses the architecture and implementation of HaL's 64-bit memory management unit (MMU). The MMU is responsible for virtual-to-physical address translations, data movement controls, bus interfaces among CPU/caches, memory subsystems; and I/O systems; and maintaining memory coherency among caches and memories.
ISSN:1063-6390
2375-0960
DOI:10.1109/CMPCON.1995.512396