Passivation cracking mechanism in high density memory devices assembled in SOJ packages adopting LOC die attach technique

The reliability tests were performed for the qualification of the high density memory devices assembled in SOJ (small outline J-leaded) packages utilizing a LOC (lead on chip) die attach technique and it was shown that the functional failure associated with a passivation break took place during T/C...

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Bibliographic Details
Main Authors: Seong-Min Lee, Jin-Hyuk Lee, Se-Yong Oh, Ho-Kyoon Chung
Format: Conference Proceeding
Language:English
Subjects:
Assembly
Lab-on-a-chip
Microassembly
Packaging
Passivation
Performance evaluation
Qualifications
Surface cracks
Testing
Thermal stresses
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Summary:The reliability tests were performed for the qualification of the high density memory devices assembled in SOJ (small outline J-leaded) packages utilizing a LOC (lead on chip) die attach technique and it was shown that the functional failure associated with a passivation break took place during T/C (thermal cycling) tests. To give a great insight into the passivation cracking phenomenon, a mechanism related to it was established through stress simulation and it was shown that the double-sided adhesive tape used for the attachment of the leadframe to the chip surface plays a significant role in defining degree of the passivation damage. The effect of the adhesive tape on the passivation damage was experimentally verified. Based on the established mechanism it is also discussed how the physical properties or the dimension of the LOC packaging materials influence the thermomechanical stability of the memory device and a proper design rule is suggested for the improvement of LOC package reliability.
DOI:10.1109/ECTC.1995.515321