Self-timed torus network with 1-of-5 encoding

Nowadays, MPSoCs or multicore processors have been becoming the major trend of system or processor designs. Thus the design of interconnection networks becomes the most important issue of all. However, lots of different problems may arise in the network design and they should be carefully handled. I...

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Bibliographic Details
Main Authors: Yuan-Teng Chang, Man-Chen Huang, Wei-Min Cheng, Hung-Yue Tsai, Chang-Jiu Chen, Fu-Chiung Cheng, Yuan-Hua Chu
Format: Conference Proceeding
Language:English
Subjects:
asynchronous circuit
Asynchronous circuits
Circuit simulation
Clocks
Encoding
Hardware design languages
interconnection network
muitcore
Multicore processing
Multiprocessor interconnection networks
Network topology
Routing
Signal design
SoC
torus
VLSI
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Summary:Nowadays, MPSoCs or multicore processors have been becoming the major trend of system or processor designs. Thus the design of interconnection networks becomes the most important issue of all. However, lots of different problems may arise in the network design and they should be carefully handled. It is widely known that most of these problems can be resolved easily by asynchronous circuits. But because of the difficulties of implementation, still only some real implementations of asynchronous networks. In this paper, we implemented a self-timed torus network with 1-of-5 DI encoding. The design was implemented in gate-level with Verilog HDL and synthesized with TSMC 0.13 mum technology. The simulation shows that the network can operate correctly in 63.9 MHz.
ISSN:0747-668X
2159-1423
DOI:10.1109/ISCE.2009.5156883