Static and dynamic test power reduction in scan-based testing

Static power due to leakage current will become a major source of power consumption in the nanometer technology era. In this paper, we propose a simple yet effective technique to reduce both static and dynamic power consumption in the scan test process. The leakage current is restrained by selecting...

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Bibliographic Details
Main Authors: Sying-Jyan Wang, Shun-Jie Huang, Li, K.S.-M.
Format: Conference Proceeding
Language:English
Subjects:
Circuit testing
CMOS logic circuits
CMOS technology
Computer science
Energy consumption
Leakage current
Power dissipation
Power engineering and energy
SPICE
Transistors
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Summary:Static power due to leakage current will become a major source of power consumption in the nanometer technology era. In this paper, we propose a simple yet effective technique to reduce both static and dynamic power consumption in the scan test process. The leakage current is restrained by selecting a good primary input vector to control the paths of leakage current during the scan shift process, and this vector can also be used to reduce dynamic power. However, the reverse is not always true. A heuristic algorithm is presented to find such vectors. The proposed method is simulated by SPICE with BPTM 22 nm transistor model, and the results show that on the average 15% total power reduction is achievable by the proposed method.
DOI:10.1109/VDAT.2009.5158094