Reliability of planar and FinFET SONOS devices for NAND flash applications - Field enhancement vs. barrier engineering

• Main Authors: Tzu-Hsuan Hsu, Hang-Ting Lue, Sheng-Chih Lai, Ya-Chin King, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu
• Format: Conference Proceeding
• Language: English
• Subjects: Capacitors; Degradation; Electron traps; Electronic mail; FinFETs; Reliability engineering; SONOS devices; Testing; Thickness control; Voltage
• ISSN: 1524-766X; 2690-8174
• DOI: 10.1109/VTSA.2009.5159336

The reliability of sub-40 nm SONOS NAND devices with various tunnel oxide thickness and FinFET structures are studied for future NAND Flash application. SONOS intrinsically has slow erase speed and high erase saturation for tunnel oxide ranging from 25 to 45 Aring. Furthermore, the endurance degradation occurs very early at low P/E 20 A. Thus planar SONOS is not suitable for NAND Flash applications. On the other hand, when SONOS is applied to FinFET structure, significantly faster erase speed is obtained, owing to the field enhancement effect. However, it is still hard to erase below the initial Vt. We conclude that barrier engineering, such as BE-SONOS is more efficient in providing faster erase speed at lower erase voltages without endurance degradation. We also estimated the large density (4 Mb) array distribution of sub-40 nm SONOS and BE-SONOS devices, and found that the distribution width is quite insensitive to the tunnel oxide thickness. This suggests that for future scaled NAND devices the edge effect is more important in determining the P/E distribution than the tunnel oxide thickness variation.