Pattern recognition using N-input neuron circuits based on floating gate MOS transistors

In this paper, a neural network hardware implementation of pattern recognition using n-input neuron circuits is presented. Floating-gate MOS (FGMOS) based neuron model using four-quadrant analog multiplier with rail-to-rail linear input and FGMOS based differential comparator has been designed and s...

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Bibliographic Details
Main Authors: Keles, F., Yildirim, T.
Format: Conference Proceeding
Language:English
Subjects:
Circuit simulation
classification
FGMOS transistors
hardware implementations
Iris
Low voltage
MOSFETs
neural network
Neural network hardware
Neural networks
Neuron circuits
Neurons
Pattern recognition
Rail to rail inputs
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Summary:In this paper, a neural network hardware implementation of pattern recognition using n-input neuron circuits is presented. Floating-gate MOS (FGMOS) based neuron model using four-quadrant analog multiplier with rail-to-rail linear input and FGMOS based differential comparator has been designed and simulated in HSPICE environment. Using the proposed low voltage neuron circuits a neural network was realized. Iris plant data set, which is one of the most well-known pattern recognition databases, was applied to test accuracy of the network.
DOI:10.1109/EURCON.2009.5167634