Low complexity synchronization design of an OFDM receiver for DVB-T/H

In this paper, an OFDM baseband receiver for DVB-T/H is presented. The receiver contains four synchronizations, an OFDM symbol synchronization, a carrier synchronization, a sampling clock synchronization and a scattered pilots synchronization. This paper proposes several novel designs to reduce the...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on consumer electronics 2009-05, Vol.55 (2), p.408-413
Main Authors: Wei, Ting-Chen, Liu, Wei-Chang, Tseng, Chi-Yao, Jou, Shyh-Jye
Format: Article
Language:English
Subjects:
Baseband
Carriers
Channel estimation
Clock synchronization
Clocks
Complexity
Delay
Digital video broadcasting
DVB
Gates
Hardware
OFDM
Orthogonal Frequency Division Multiplexing
Pilots
Receivers
Sampling methods
Scattering
Synchronism
Synchronization
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, an OFDM baseband receiver for DVB-T/H is presented. The receiver contains four synchronizations, an OFDM symbol synchronization, a carrier synchronization, a sampling clock synchronization and a scattered pilots synchronization. This paper proposes several novel designs to reduce the synchronization latency and hardware complexity. The carrier and clock synchronization loops are fully digitalized schemes. The scattered pilots synchronization adopts a two stages scheme to reduce the detection latency. In addition, the pre-filling scheme reduces the latency of channel estimation. The design result shows that the equivalent gate count is about 810 K gates including 102.8 KB memory.
ISSN:0098-3063
1558-4127
DOI:10.1109/TCE.2009.5174401