Architecture design of MPEG-2 decoder system

An architecture for the VLSI design of an MPEG-2 video decoder is introduced to achieve the MP@ML (main profile, main level). The hardware complexity is analyzed, and the decoding unit is designed to reach the required performance. The decoding unit includes variable length decoding (VLD), inverse s...

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Bibliographic Details
Main Authors: Yung-Pin Lee, Liang-Gee Chen, Chung-Wei Ku
Format: Conference Proceeding
Language:English
Subjects:
Bit rate
Buffer storage
Decoding
Delay
Hardware
HDTV
Random access memory
Scalability
Transform coding
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Summary:An architecture for the VLSI design of an MPEG-2 video decoder is introduced to achieve the MP@ML (main profile, main level). The hardware complexity is analyzed, and the decoding unit is designed to reach the required performance. The decoding unit includes variable length decoding (VLD), inverse scan, inverse quantization (IQ), IDCT, and motion compensation.
DOI:10.1109/ICCE.1995.517978