A single-chip concatenated FEC decoder

A single chip decoder, which implements the concatenated forward error correction functions for a digital satellite receiver system, has been designed. The functions include Viterbi decoding, convolutional deinterleaving, Reed-Solomon decoding, data stream synchronization and descrambling. The devic...

Full description

Saved in:
Bibliographic Details
Main Authors: Luthi, D.A., Mogre, A., Ben-Efraim, N., Gupta, A.
Format: Conference Proceeding
Language:English
Subjects:
CMOS technology
Concatenated codes
Convolutional codes
Decoding
Digital video broadcasting
Forward error correction
Quadrature phase shift keying
Reed-Solomon codes
Satellites
Viterbi algorithm
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A single chip decoder, which implements the concatenated forward error correction functions for a digital satellite receiver system, has been designed. The functions include Viterbi decoding, convolutional deinterleaving, Reed-Solomon decoding, data stream synchronization and descrambling. The device has been fabricated in a 0.6 /spl mu/m CMOS cell-based technology and is fully functional at data rates of 73 Mbits/sec at 70/spl deg/C and 4.75 V.
DOI:10.1109/CICC.1995.518187