Concurrent logic and layout design system for high performance LSIs

This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application result...

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Bibliographic Details
Main Authors: Murakata, M., Murofushi, M., Igarashi, M., Aoki, T., Ishioka, T., Mitsuhashi, T., Goto, N.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Delay estimation
Design methodology
Design optimization
Integrated circuit interconnections
Large scale integration
Logic design
Power system interconnection
Timing
Wire
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Description
Summary:This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application results show that this system realized high performance LSIs over 100 MHz without logic-layout design iteration.
DOI:10.1109/CICC.1995.518225