Concurrent logic and layout design system for high performance LSIs

This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application result...

Full description

Saved in:
Bibliographic Details
Main Authors: Murakata, M., Murofushi, M., Igarashi, M., Aoki, T., Ishioka, T., Mitsuhashi, T., Goto, N.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Delay estimation
Design methodology
Design optimization
Integrated circuit interconnections
Large scale integration
Logic design
Power system interconnection
Timing
Wire
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 468
container_issue
container_start_page 465
container_title
container_volume
creator Murakata, M.
Murofushi, M.
Igarashi, M.
Aoki, T.
Ishioka, T.
Mitsuhashi, T.
Goto, N.
description This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application results show that this system realized high performance LSIs over 100 MHz without logic-layout design iteration.
doi_str_mv 10.1109/CICC.1995.518225
format conference_proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_518225</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>518225</ieee_id><sourcerecordid>518225</sourcerecordid><originalsourceid>FETCH-LOGICAL-i104t-81905fd48d7293c5b4044f95056b6c47d9d9675a3a8e2e7ac0af152932695b503</originalsourceid><addsrcrecordid>eNotT0trwzAYM4xBR5f76Ml_IJnt-Ivt4zB7BAI9bDsXx3ZSjzyKnR7y75fRCYF0EEJC6ImSglKinnWtdUGVggKoZAzuUKaEJBtLBpLDDmUp_ZANHAhU4gFpPU_2GqOfFjzMfbDYTA4PZp2vC3Y-hX7CaU2LH3E3R3wO_RlffNz8aCbrcfNZp0d035kh-exf9-j77fVLf-TN8b3WL00eKOFLLqki0DkunWCqtNBywnmn_oa0leXCKacqAaY00jMvjCWmo7BFWaWgBVLu0eHWG7z3p0sMo4nr6fa0_AXJjEf1</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Concurrent logic and layout design system for high performance LSIs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Murakata, M. ; Murofushi, M. ; Igarashi, M. ; Aoki, T. ; Ishioka, T. ; Mitsuhashi, T. ; Goto, N.</creator><creatorcontrib>Murakata, M. ; Murofushi, M. ; Igarashi, M. ; Aoki, T. ; Ishioka, T. ; Mitsuhashi, T. ; Goto, N.</creatorcontrib><description>This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application results show that this system realized high performance LSIs over 100 MHz without logic-layout design iteration.</description><identifier>ISBN: 9780780325845</identifier><identifier>ISBN: 0780325842</identifier><identifier>DOI: 10.1109/CICC.1995.518225</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; Delay estimation ; Design methodology ; Design optimization ; Integrated circuit interconnections ; Large scale integration ; Logic design ; Power system interconnection ; Timing ; Wire</subject><ispartof>Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995, p.465-468</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/518225$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/518225$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Murakata, M.</creatorcontrib><creatorcontrib>Murofushi, M.</creatorcontrib><creatorcontrib>Igarashi, M.</creatorcontrib><creatorcontrib>Aoki, T.</creatorcontrib><creatorcontrib>Ishioka, T.</creatorcontrib><creatorcontrib>Mitsuhashi, T.</creatorcontrib><creatorcontrib>Goto, N.</creatorcontrib><title>Concurrent logic and layout design system for high performance LSIs</title><title>Proceedings of the IEEE 1995 Custom Integrated Circuits Conference</title><addtitle>CICC</addtitle><description>This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application results show that this system realized high performance LSIs over 100 MHz without logic-layout design iteration.</description><subject>Capacitance</subject><subject>Delay estimation</subject><subject>Design methodology</subject><subject>Design optimization</subject><subject>Integrated circuit interconnections</subject><subject>Large scale integration</subject><subject>Logic design</subject><subject>Power system interconnection</subject><subject>Timing</subject><subject>Wire</subject><isbn>9780780325845</isbn><isbn>0780325842</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1995</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotT0trwzAYM4xBR5f76Ml_IJnt-Ivt4zB7BAI9bDsXx3ZSjzyKnR7y75fRCYF0EEJC6ImSglKinnWtdUGVggKoZAzuUKaEJBtLBpLDDmUp_ZANHAhU4gFpPU_2GqOfFjzMfbDYTA4PZp2vC3Y-hX7CaU2LH3E3R3wO_RlffNz8aCbrcfNZp0d035kh-exf9-j77fVLf-TN8b3WL00eKOFLLqki0DkunWCqtNBywnmn_oa0leXCKacqAaY00jMvjCWmo7BFWaWgBVLu0eHWG7z3p0sMo4nr6fa0_AXJjEf1</recordid><startdate>1995</startdate><enddate>1995</enddate><creator>Murakata, M.</creator><creator>Murofushi, M.</creator><creator>Igarashi, M.</creator><creator>Aoki, T.</creator><creator>Ishioka, T.</creator><creator>Mitsuhashi, T.</creator><creator>Goto, N.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1995</creationdate><title>Concurrent logic and layout design system for high performance LSIs</title><author>Murakata, M. ; Murofushi, M. ; Igarashi, M. ; Aoki, T. ; Ishioka, T. ; Mitsuhashi, T. ; Goto, N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-81905fd48d7293c5b4044f95056b6c47d9d9675a3a8e2e7ac0af152932695b503</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Capacitance</topic><topic>Delay estimation</topic><topic>Design methodology</topic><topic>Design optimization</topic><topic>Integrated circuit interconnections</topic><topic>Large scale integration</topic><topic>Logic design</topic><topic>Power system interconnection</topic><topic>Timing</topic><topic>Wire</topic><toplevel>online_resources</toplevel><creatorcontrib>Murakata, M.</creatorcontrib><creatorcontrib>Murofushi, M.</creatorcontrib><creatorcontrib>Igarashi, M.</creatorcontrib><creatorcontrib>Aoki, T.</creatorcontrib><creatorcontrib>Ishioka, T.</creatorcontrib><creatorcontrib>Mitsuhashi, T.</creatorcontrib><creatorcontrib>Goto, N.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Murakata, M.</au><au>Murofushi, M.</au><au>Igarashi, M.</au><au>Aoki, T.</au><au>Ishioka, T.</au><au>Mitsuhashi, T.</au><au>Goto, N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Concurrent logic and layout design system for high performance LSIs</atitle><btitle>Proceedings of the IEEE 1995 Custom Integrated Circuits Conference</btitle><stitle>CICC</stitle><date>1995</date><risdate>1995</risdate><spage>465</spage><epage>468</epage><pages>465-468</pages><isbn>9780780325845</isbn><isbn>0780325842</isbn><abstract>This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application results show that this system realized high performance LSIs over 100 MHz without logic-layout design iteration.</abstract><pub>IEEE</pub><doi>10.1109/CICC.1995.518225</doi><tpages>4</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 9780780325845
ispartof Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995, p.465-468
issn
language eng
recordid cdi_ieee_primary_518225
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Capacitance
Delay estimation
Design methodology
Design optimization
Integrated circuit interconnections
Large scale integration
Logic design
Power system interconnection
Timing
Wire
title Concurrent logic and layout design system for high performance LSIs
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T02%3A52%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Concurrent%20logic%20and%20layout%20design%20system%20for%20high%20performance%20LSIs&rft.btitle=Proceedings%20of%20the%20IEEE%201995%20Custom%20Integrated%20Circuits%20Conference&rft.au=Murakata,%20M.&rft.date=1995&rft.spage=465&rft.epage=468&rft.pages=465-468&rft.isbn=9780780325845&rft.isbn_list=0780325842&rft_id=info:doi/10.1109/CICC.1995.518225&rft_dat=%3Cieee_6IE%3E518225%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i104t-81905fd48d7293c5b4044f95056b6c47d9d9675a3a8e2e7ac0af152932695b503%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=518225&rfr_iscdi=true