Cost-Effective 28-nm LSTP CMOS using gate-first metal gate/high-k technology

Metal gate/high-k CMOS technology for 28-nm node low power and low standby power application is demonstrated. A gate-first single metal/high-k gate stack has been employed together with leading-edge isolation, ultra-shallow junction, and stress engineering technologies. High density and high perform...

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Main Authors: Tomimatsu, T., Goto, Y., Kato, H., Amma, M., Igarashi, M., Kusakabe, Y., Takeuchi, M., Ohbayashi, S., Sakashita, S., Kawahara, T., Mizutani, M., Inoue, M., Sawada, M., Kawasaki, Y., Yamanari, S., Miyagawa, Y., Takeshima, Y., Yamamoto, Y., Endo, S., Hayashi, T., Nishida, Y., Horita, K., Yamashita, T., Oda, H., Tsukamoto, K., Inoue, Y., Fujimoto, H., Sato, Y., Yamashita, K., Mitsuhashi, R., Matsuyama, S., Moriyama, Y., Nakanishi, K., Noda, T., Sahara, Y., Koike, N., Hirase, J., Yamada, T., Ogawa, H., Ogura, M.
Format: Conference Proceeding
Language:English
Subjects:
CMOS technology
High K dielectric materials
High-K gate dielectrics
Intrusion detection
Isolation technology
Leakage current
MOS devices
MOSFETs
Stress
Surface-mount technology
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Summary:Metal gate/high-k CMOS technology for 28-nm node low power and low standby power application is demonstrated. A gate-first single metal/high-k gate stack has been employed together with leading-edge isolation, ultra-shallow junction, and stress engineering technologies. High density and high performance device is provided with least process cost increase.
ISSN:0743-1562