Design of floating point units for interval arithmetic

In this paper, hardware units for interval addition, multiplication and divide-add fused are presented. Regarding interval addition, a new architecture of double path adder, is presented. This architecture exploits the parallel structure of double path adder. Regarding multiplication, the proposed a...

Full description

Saved in:
Bibliographic Details
Main Authors: Amaricai, A., Vladutiu, M., Boncalo, O.
Format: Conference Proceeding
Language:English
Subjects:
Adders
Computer architecture
Costs
Delay
Floating-point arithmetic
H infinity control
Hardware
Newton method
Nonlinear equations
Standards development
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper, hardware units for interval addition, multiplication and divide-add fused are presented. Regarding interval addition, a new architecture of double path adder, is presented. This architecture exploits the parallel structure of double path adder. Regarding multiplication, the proposed architecture is based on a dual result multiplier (floating point multiplication unit with two differently rounded results for the same pair of operands) and two floating point comparators. The goal of the divide-add fused unit is to increase the performance of the interval Newton's method. Algorithm and architecture for this operation, inspired by the ones used for multiply-add fused, are proposed.
DOI:10.1109/RME.2009.5201307